Grid array packages

ABSTRACT

A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the second surface, and substrate pads on the second surface, adjacent to the opening. Bond pads of the semiconductor die are aligned with the opening through the substrate. Intermediate conductive elements, such as bond wires, extend from bond pads of the semiconductor die, through the opening, to substrate pads on the opposite, second surface of the substrate. An encapsulant, which fills the opening and covers the intermediate conductive elements, protrudes beyond a plane in which the second surface of the substrate is located. Discrete conductive elements, such as solder balls, may protrude from the contact pads of the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/866,065, filed Oct. 2, 2007, which is a continuation of U.S. patentapplication Ser. No. 11/437,550, filed May 19, 2006, now U.S. Pat. No.7,381,591, issued Jun. 3, 2008, which is a continuation of U.S. patentapplication Ser. No. 11/070,364, filed Mar. 1, 2005, now U.S. Pat. No.7,329,945, issued Feb. 12, 2008, which is a continuation of U.S. patentapplication Ser. No. 09/699,537, filed Oct. 30, 2000, now U.S. Pat. No.6,861,290, issued Mar. 1, 2005, which is a divisional of U.S. patentapplication Ser. No. 09/483,483, filed Jan. 14, 2000, now U.S. Pat. No.6,265,766, issued Jul. 24, 2001, which is a continuation of U.S. patentapplication Ser. No. 08/948,936, filed Oct. 10, 1997, now U.S. Pat. No.6,201,304, issued Mar. 13, 2001, which is a continuation of U.S. patentapplication Ser. No. 08/574,662, filed Dec. 19, 1995, now U.S. Pat. No.5,719,440, issued Feb. 17, 1998. The disclosure of each of thepreviously referenced U.S. patent applications and patents is herebyincorporated herein by this reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus for connecting a baresemiconductor die having a size and bond pad arrangement, either solderball arrangement, or pin arrangement (hereinafter referred to generallyas a “terminal arrangement”), which does not conform to a printedcircuit board with a specific or standardized pin out, connector pad, orlead placement (hereinafter referred to generally as a “connectionarrangement”). More particularly, the present invention relates to anintermediate conductor-carrying substrate (hereinafter referred togenerally as an “adaptor board”) for connecting a non-conforming baredie to another printed circuit board having a given connectionarrangement (hereinafter referred to generally as a “master board”).

2. State of the Art

Definitions: The following terms and acronyms will be used throughoutthe application and are defined as follows:

BGA—Ball Grid Array: An array of minute solder balls disposed on anattachment surface of a semiconductor die wherein the solder balls arerefluxed for simultaneous attachment and electrical communication of thesemiconductor die to a printed circuit board.

COB—Chip On Board: The techniques used to attach-semiconductor dice to aprinted circuit board, including flip-chip attachment, wire bonding, andtape automated bonding (“TAB”).

Flip-Chip: A chip or die that has bumped terminations spaced around theactive surface of the die and is intended for facedown mounting.

Flip-Chip Attachment: A method of attaching a semiconductor die to asubstrate in which the die is flipped so that the connecting conductorpads on the face of the die are set on mirror-image pads on thesubstrate (i.e., printed circuit board) and bonded by refluxing thesolder.

Glob Top: A glob of encapsulant material (usually epoxy or silicone or acombination thereof) surrounding a semiconductor die in the COB assemblyprocess.

PGA—Pin Grid Array: An array of small pins extending substantiallyperpendicularly from the major plane of a semiconductor die, wherein thepins conform to a specific arrangement on a printed circuit board forattachment thereto.

SLICC—Slightly Larger than Integrated Circuit Carrier: An array ofminute solder balls disposed on an attachment surface of a semiconductordie similar to a BGA, but having a smaller solder ball pitch anddiameter than a BGA.

State-of-the-art COB technology generally consists of threesemiconductor die to printed circuit board attachment techniques:flip-chip attachment, wire bonding, and TAB.

Flip-chip attachment consists of attaching a semiconductor die,generally having a BGA, a SLICC or a PGA, to a printed circuit board.With the BGA or SLICC, the solder ball arrangement on the semiconductordie must be a mirror-image of the connecting bond pads on the printedcircuit board such that precise connection is made. The semiconductordie is bonded to the printed circuit board by refluxing the solderballs. With the PGA, the pin arrangement of the semiconductor die mustbe a mirror-image of the pin recesses on the printed circuit board.After insertion, the semiconductor die is generally bonded by solderingthe pins into place. An under-fill encapsulant is generally disposedbetween the semiconductor die and the printed circuit board to preventcontamination. A variation of the pin-in-recess PGA is a J-lead PGA,wherein the loops of the Js are soldered to pads on the surface of thecircuit board. Nonetheless, the lead and pad locations must coincide, aswith the other referenced flip-chip techniques.

Wire bonding and TAB attachment generally begins with attaching asemiconductor die to the surface of a printed circuit board with anappropriate adhesive. In wire bonding, a plurality of bond wires areattached, one at a time, from each bond pad on the semiconductor die andto a corresponding lead on the printed circuit board. The bond wires aregenerally attached through one of three industry-standard wire bondingtechniques: ultrasonic bonding, using a combination of pressure andultrasonic vibration bursts to form a metallurgical cold weld;thermocompression bonding, using a combination of pressure and elevatedtemperature to form a weld; and thermosonic bonding, using a combinationof pressure, elevated temperature, and ultrasonic vibration bursts. Thedie may be oriented either face up or face down (with its active surfaceand bond pads either up or down with respect to the circuit board) forwire bonding, although face up orientation is more common. With TAB,metal tape leads are attached between the bond pads on the semiconductordie and the leads on the printed circuit board. An encapsulant isgenerally used to cover the bond wires and metal tape leads to preventcontamination.

Although the foregoing methods are effective for bonding semiconductordice to printed circuit boards, the terminal arrangements of the diceand the connection arrangements of the boards must be designed toaccommodate one another. Thus, it may be impossible to electricallyconnect a particular semiconductor die to a printed circuit board forwhich the semiconductor die terminal arrangement was not designed tomatch the board's connection arrangement. With either wire bond or TABattachment, the semiconductor die bond pad may not correspond to thelead ends on the circuit board, and thus attachment is either impossibleor extremely difficult due to the need for overlong wires and thepotential for inter-wire contact and shorting. With flip-chipattachment, if the printed circuit board connection arrangement is not amirror-image of the solder ball or pin arrangement (terminalarrangement) on the semiconductor die, electrically connecting theflip-chip to the printed circuit board is impossible.

Therefore, it would be advantageous to develop an apparatus forconnecting a semiconductor die having a size and bond pad arrangement,solder ball arrangement, or pin arrangement (“I/O pattern”) which doesnot conform to a printed circuit board with a specific or standardizedpin out, connection pad location, or lead placement (“I/O pattern”).

SUMMARY OF THE INVENTION

The present invention relates to an intermediate printed circuit boardor other conductor-carrying substrate that functions as an adaptor boardfor electrically connecting one or more bare semiconductor dice of avariety of sizes and bond pad locations, solder ball arrangement, or pinarrangement, to a master printed circuit board with a specific orstandardized pin out, connector pad location, or lead placement.

An adaptor printed circuit board or substrate (“adaptor board”) is sizedand configured with an I/O pattern to accommodate its attachment to themaster printed circuit board (“master board”). If the master board isconfigured to receive a specific pin out or specific connector padlocations, the adaptor board is configured on its master boardattachment surface with pins or solder balls in mirror-image to themaster board connection arrangement to make electrical contact with thespecific pin out or connector pads on the printed circuit board. If themaster board is configured to receive a bond wire, the adaptor board isconfigured and sized to provide wire bond pads on its upper surfaceclosely adjacent the bond pads of the master board leads. The adaptorboard can, of course, be configured to accommodate other attachment andelectrical connection means known in the industry, as well as othercomponents in addition to the semiconductor die or dice carried thereon.

On the semiconductor die side of the adaptor board, one or moresemiconductor dice are attached. If a “flip-chip” die is attached to theadaptor board, the adaptor board will, of course, be configured with anI/O pattern to receive the flip-chip with a specific pin out orconnector pad locations. The pin out or connector pads on the adaptorboard are connected to circuit traces on or through the adaptor board.The circuit traces form the electrical communication path from the pinrecesses or connector pads on the adaptor board to the connection pointsto the master board.

If a “leads over” die is used with the adaptor board, the bond pads onthe die are wire bonded to the adaptor board. Preferably, the leads overdie is attached to the adaptor board with the bond pads facing theadaptor board. The bond wires are attached to the leads over die bondpads and extend into a via or vias in the adaptor board. The bond wiresare attached to an I/O pattern of adaptor board bond pads within the viafrom which circuit traces extend, or to leads on the master board sideof the adaptor board.

It is, of course, understood that the leads over die can be attached tothe adaptor board with the bond pads facing away from the adaptor board.Thus, the bond wires are simply attached to the bond pads on the leadsover die and to a corresponding I/O pattern of adaptor board pad on thesemiconductor die side of the adaptor board.

Preferably, the exposed circuitry of the die and the die-to-adaptorboard interconnection is sealed from contamination by a glob top afterwire bonding or an underflow compound in the case of a flip-chipattachment.

Furthermore, it is understood that with the use of wire bonds, theadaptor boards can be stacked on top of each other and connected to theadaptor board as by wire bonding.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,the advantages of this invention can be more readily ascertained fromthe following description of the invention when read in conjunction withthe accompanying drawings in which:

FIG. 1 is a side view of one embodiment of the present invention;

FIG. 2 is a side view of a second embodiment of the present invention;

FIG. 2A is a top view of the second embodiment of the present inventionshown in FIG. 2;

FIG. 3 is a side view of a third embodiment of the present invention;

FIG. 3A is an upside-down exploded perspective view of selected portionsof the third embodiment; and

FIG. 4 is a side view of a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a first embodiment of the present inventiondesignated as a flip-chip style/flip-chip attachment assembly 100.Assembly 100 comprises a semiconductor die 12 having an inverted activesurface 14 with at least one flip-chip electric connection 16 (such as aC4 solder bump connection, a pin connection, or a surface mount J-leadconnection, by way of example) extending substantially perpendicularlyfrom a bond pad 15 on the semiconductor die active surface 14. Theflip-chip electric connections 16 are attached to an upper surface 20 ofan adaptor board 18 in such a manner that the flip-chip electricconnections 16 make electrical contact with electrical contact elements21 in or on the surface of adaptor board 18. The electrical contactelements 21 make electrical communication between each flip-chipelectric connection 16, through circuit traces 23 (exemplary tracesshown in broken lines) in the adaptor board 18, to at least one masterboard connector 22 extending substantially perpendicularly from a lowersurface 24 of the adaptor board 18 to connect adaptor board 18 to analigned terminal 31 on master board 30. Preferably, a sealing compound26 is disposed between the semiconductor die 12 and the adaptor board 18to prevent contamination of the flip-chip electric connections 16 and tomore firmly secure semiconductor die 12 to adaptor board 18.

In actual practice, there will be a plurality of terminals 31 arrangedin a specific, perhaps industry-standard pattern, on master board 30,and master board connectors 22 will be arranged in a mirror-imagepattern to terminals 31 for mating connection therewith. Master boardconnectors 22 and terminals 31 may comprise any electrical connectionmechanism known in the art, in addition to those previously describedherein.

FIGS. 2 and 2A illustrate a second embodiment of the present inventiondesignated as a flip-chip style/wire bond attachment assembly 200.Components common to both FIG. 1 and FIG. 2 retain the same numericdesignation. The assembly 200 comprises the semiconductor die 12 havingactive surface 14 with at least one flip-chip electric connection 16, asknown in the art, extending substantially perpendicularly from a bondpad 15 on the semiconductor die active surface 14. The flip-chipelectric connections 16 are attached to the adaptor board upper surface20 in such a manner that the flip-chip electric connections 16 makeelectrical contact with electrical contact elements 21 on the adaptorboard 18. The electrical contact elements 21 communicate between eachflip-chip electric connection 16 to bond pads 28 on the adaptor boardupper surface 20 through circuit traces 23. The adaptor board lowersurface 24 is bonded to an upper surface 36 of a master board 30 with anadhesive 32, which may comprise a liquid or gel adhesive, or an adhesivetape, all as known in the art. If desired, adhesive 32 may be aheat-conductive adhesive. A wire bond 34 extends from each adaptor boardbond pad 28 to a corresponding bond pad or lead end 35 on the uppersurface 36 of master board 30, bond pad or lead end 35 communicatingwith other components mounted to master board 30 or with othercomponents on other boards or other assemblies through circuit traces orother conductors known in the art.

FIGS. 3 and 3A illustrate a third embodiment of the present inventiondesignated as a wire bond style/flip-chip attachment assembly 300.Components which are common to the previous figures retain the samenumeric designation. The assembly 300 comprises an invertedsemiconductor die 12 having active surface 14 with at least one bond pad38 on the semiconductor die active surface 14. As illustrated, the bondpads 38 are arranged in two rows extending down the longitudinal axis ofsemiconductor die 12 being located transverse to the plane of the page,such an arrangement commonly being used for a “leads over” connection toframe leads extending over the die in its normal, upright position. Thesemiconductor die active surface 14 is bonded to the adaptor board uppersurface 20 with an insulating, sealing adhesive 40. The adaptor board 18includes at least one or more wire bond vias 42 which is located in aposition or positions aligned with the semiconductor die bond pads 38.Each individual wire bond 134 is connected to each correspondingindividual semiconductor die bond pad 38. Each wire bond 134 extendsfrom the semiconductor die bond pad 38 to a corresponding bond pad orlead 39 on the adaptor board lower surface 24, which communicates withmaster board connectors 22 through circuit traces 23. The master boardterminals 31 are in electrical communication with at least one masterboard connector 22 extending substantially perpendicularly from theadaptor board lower surface 24. Preferably, a sealant 44 encases thebond wires 134 and seals the wire bond via 42 to prevent contaminationand damage to the wire bonds.

FIG. 4 illustrates a fourth embodiment of the present inventiondesignated as a wire bond style/wire bond attachment assembly 400.Components which are common to the previous figures retain the samenumeric designation. The assembly 400 comprises the semiconductor die 12having active surface 14 with at least one bond pad 38 on thesemiconductor die active surface 14. As with the embodiment of FIG. 3,semiconductor die 12 in this instance employs bond pads 38 in a “leadsover” configuration. The semiconductor die active surface 14 is bondedto the adaptor board upper surface 20 with an insulating, sealingadhesive 40. The adaptor board 18 includes at least one or more wirebond vias 42 which are located in a position or positions aligned withthe semiconductor die bond pads 38. Each individual wire bond 134 isconnected to each corresponding semiconductor die bond pad 38. Each wirebond 134 extends from the semiconductor die bond pad 38 to acorresponding bond pad 46 within the wire bond via 42. The via bond pads46 are in electrical communication through circuit traces 23 with atleast one corresponding adaptor board bond pad 28. The adaptor boardlower surface 24 is bonded to the master board upper surface 36 with theadhesive 32. Wire bonds 34 extend from the adapter board upper surface20 to a corresponding bond pad or lead end 35 on the master board uppersurface 36. Preferably, the wire bond via sealant 44 encases the bondwires 134 and seals the wire bond via 42 to prevent contamination.

Having thus described in detail preferred embodiments of the presentinvention, it is to be understood that the invention defined by theappended claims is not to be limited by particular details set forth inthe above description as many apparent variations thereof are possiblewithout departing from the spirit or scope thereof.

1. A semiconductor device, comprising: a substrate with no more than oneopening therethrough, the opening elongated along a center axis of thesubstrate, the substrate otherwise being substantially uniform inthickness and further comprising a first surface, a second surfaceopposite the first surface, a first row of substrate pads adjacent to afirst side of the opening on the second surface, second row of substratepads adjacent to a second side of the opening on the second surface, anda circuit trace extending through the substrate from each substrate padto a trace terminal on the second surface; a semiconductor diecomprising die pads on an active surface; an adhesive material securingthe semiconductor die to the first surface of the substrate with theactive surface of the semiconductor die facing the first surface of thesubstrate; bond wires extending from the die pads, through the opening,and to the first and second rows of substrate pads; an encapsulantsubstantially filling the opening, the encapsulant covering the bondwires and protruding a first distance beyond a plane of the secondsurface of the substrate forming a protrusion beneath the opening,wherein the protrusion protrudes a first profile distance from thesecond surface; and solder balls located on the second surface and eachsolder ball being in contact with one of the trace terminals, inelectrical communication with the first and second rows of substratepads via the corresponding circuit traces and in electricalcommunication with the die pads via the bond wires, and protruding fromthe second surface a second profile distance, with the second profiledistance exceeding the first profile distance.
 2. The semiconductordevice of claim 1, wherein the die pads of the semiconductor dieinclude: a first row of die pads in electrical communication with thefirst row of substrate pads; and a second row of die pads in electricalcommunication with the second row of substrate pads.
 3. Thesemiconductor device of claim 2, wherein the first and second sides ofthe opening of the substrate are parallel to each other.
 4. Thesemiconductor device of claim 3, wherein the substrate lacks substratepads adjacent to ends of the opening.
 5. The semiconductor device ofclaim 1, wherein the adhesive extends beyond an outer periphery of thesemiconductor die.
 6. The semiconductor device of claim 5, wherein theadhesive does not extend beyond a periphery of the opening of thesubstrate.
 7. The semiconductor device of claim 1, wherein the adhesivedoes not extend beyond a periphery of the opening of the substrate. 8.The semiconductor device of claim 1, wherein at least some of the solderballs are located in positions on the second surface of the substratewith which the semiconductor die adjacent to the first surface of thesubstrate is not superimposed.
 9. The semiconductor device of claim 8,wherein at least some of the solder balls are located at positions onthe second surface of the substrate with which the semiconductor dieadjacent to the first surface of the substrate is superimposed.
 10. Thesemiconductor device of claim 9, wherein a majority of the solder ballsare located at positions on the second surface of the substrate withwhich the semiconductor die adjacent to the first surface of thesubstrate is superimposed.
 11. The semiconductor device of claim 1,wherein at least some of the solder balls are located at positions onthe second surface of the substrate with which the semiconductor dieadjacent to the first surface of the substrate is superimposed.
 12. Thesemiconductor device of claim 1, further comprising: a master printedcircuit board including connector pads to which the solder balls aresoldered, the master printed circuit board including conductive tracesfor establishing electrical communication between the connector pads andelectrical components mounted to the master printed circuit board. 13.The semiconductor device of claim 1, wherein the substrate has asubstantially planar first surface and at least one lateral dimensionthat exceeds a corresponding lateral dimension of the semiconductor die.14. The semiconductor device of claim 13, wherein a portion of thesubstrate extends laterally beyond an outer periphery of thesemiconductor die.
 15. The semiconductor device of claim 1, wherein theopening of the substrate has a length at least as long as acorresponding dimension of the semiconductor die.
 16. The semiconductordevice of claim 15, wherein the opening of the substrate extends atleast from one outer peripheral edge of the semiconductor die to anopposite outer peripheral edge of the semiconductor die.
 17. Thesemiconductor device of claim 1, wherein the solder balls include: afirst three rows of solder balls arranged parallel to the center axis ofthe substrate, in a first region of the second surface of the substrate,the first region being located between the encapsulant and a first edgeof the substrate; and a second three rows of solder balls arrangedparallel to the center axis of the substrate, in a second region of thesecond surface of the substrate, the second region being located betweenthe encapsulant and a second edge of the substrate, the second edgebeing opposite from the first edge.
 18. The semiconductor device ofclaim 17, wherein the solder balls include no more than three rows ofsolder balls in the first region of the second surface of the substrateand no more than three rows of solder balls in the second region of thesecond surface of the substrate.
 19. The semiconductor device of claim17, wherein at least some of the solder balls are located at positionson the second surface of the substrate with which the semiconductor dieadjacent to the first surface of the substrate is not superimposed. 20.The semiconductor device of claim 1, wherein the encapsulant issubstantially laterally confined within a boundary over the secondsurface of the substrate surrounding the opening, and located betweenthe substrate pads and the solder balls.
 21. The semiconductor device ofclaim 1, wherein the encapsulant is substantially absent from regions ofthe second surface in a vicinity of the solder balls.
 22. Thesemiconductor device of claim 1, wherein the substrate comprises asubstantially planar substrate of sufficient rigidity to maintainplanarity in an outer peripheral region located laterally beyond anouter periphery of the semiconductor die.
 23. The semiconductor deviceof claim 22, wherein the peripheral region of the substrate is at leastas wide as a pitch between the solder balls.
 24. The semiconductordevice of claim 1, further comprising: an encapsulating material on thefirst surface of the substrate and surrounding an outer periphery of thesemiconductor die.
 25. A semiconductor device, comprising: asemiconductor die comprising die pads along a center region of an activesurface; a substrate comprising a single slot aligned with the die pads,a substantially planar first surface, a substantially planar secondsurface parallel to the first surface, first and second rows ofsubstrate pads on the substantially planar second surface, proximatefirst and second sides of the single slot, respectively, and a circuittrace extending through the substrate from each substrate pad to a traceterminal on the second surface; adhesive between the active surface ofthe die and the first surface of the substrate; bond wires that passthrough the single slot, with first ends of the bond wires bonded to thedie pads and second ends of the bond wires bonded to the first andsecond rows of substrate pads; encapsulant filling the single slot andprotruding a first distance beyond a plane in which the second surfaceof the substrate is located; and solder balls protruding a seconddistance from the second surface of the substrate and each solder ballbeing in contact with one of the trace terminals, the second distancebeing greater than the first distance, wherein the solder balls are inelectrical communication with the die pads via the trace terminals, thecircuit traces, the substrate pads and the bond wires.
 26. Thesemiconductor device of claim 25, wherein the die pads of thesemiconductor die are arranged in: a first row in electricalcommunication with the first row of substrate pads; and a second row inelectrical communication with the second row of substrate pads.
 27. Thesemiconductor device of claim 25, wherein all of the substrate pads ofthe substrate are located proximate to a first side of the single slotor a second side of the single slot.
 28. The semiconductor device ofclaim 25, wherein the adhesive extends laterally beyond an outerperiphery of the semiconductor die.
 29. The semiconductor device ofclaim 28, further comprising: another encapsulant on the first surfaceof the substrate and surrounding an outer periphery of the semiconductordie.
 30. The semiconductor device of claim 28, wherein the adhesive issubstantially laterally confined outside of an interior periphery of thesubstrate that defines the single slot.
 31. The semiconductor device ofclaim 25, wherein the adhesive is substantially laterally confinedoutside of an interior periphery of the substrate that defines thesingle slot.
 32. The semiconductor device of claim 25, wherein at leastsome of the solder balls are located at positions on the second surfaceof the substrate with which the semiconductor die adjacent to the firstsurface of the substrate is not superimposed.
 33. The semiconductordevice of claim 32, wherein a majority of the solder balls are locatedat positions on the second surface of the substrate with which thesemiconductor die adjacent to the first surface of the substrate issuperimposed.
 34. The semiconductor device of claim 25, wherein amajority of the solder balls are located at positions on the secondsurface of the substrate with which the semiconductor die adjacent tothe first surface of the substrate is superimposed.
 35. Thesemiconductor device of claim 25, further comprising: a printed circuitboard including connector pads to which the solder balls are soldered,the printed circuit board including conductive traces for establishingelectrical communication between the connector pads and electricalcomponents mounted to the printed circuit board.
 36. The semiconductordevice of claim 25, wherein the substrate is of sufficient rigidity tomaintain planarity in an outer peripheral region located laterallybeyond an outer periphery of the semiconductor die.
 37. Thesemiconductor device of claim 36, wherein the peripheral region of thesubstrate is at least as wide as a pitch between the solder balls. 38.The semiconductor device of claim 25, wherein the single slot of thesubstrate has a length at least as long as a corresponding dimension ofthe semiconductor die.
 39. The semiconductor device of claim 38, whereinthe single slot of the substrate extends at least from one outerperipheral edge of the semiconductor die to an opposite outer peripheraledge of the semiconductor die.
 40. The semiconductor device of claim 39,wherein the substrate is of sufficient rigidity to maintain planarity inan outer peripheral region located laterally beyond an outer peripheryof the semiconductor die.
 41. The semiconductor device of claim 25,wherein the solder balls are arranged in: a first three rows parallel tothe single slot of the substrate, in a first region of the secondsurface of the substrate, the first region being located between theencapsulant and a first edge of the substrate; and a second three rowsparallel to the single slot of the substrate, in a second region of thesecond surface of the substrate, the second region being located betweenthe encapsulant and a second edge of the substrate, the second edgebeing opposite from the first edge.
 42. The semiconductor device ofclaim 41, wherein no more than three rows of solder balls are located inthe first region of the second surface of the substrate and no more thanthree rows of solder balls are located in the second region of thesecond surface of the substrate.
 43. The semiconductor device of claim41, wherein at least some of the solder balls are located at positionson the second surface of the substrate with which the semiconductor dieadjacent to the first surface of the substrate is not superimposed. 44.The semiconductor device of claim 25, wherein the encapsulant issubstantially laterally confined within a boundary over the secondsurface of the substrate surrounding the single slot, and locatedbetween the substrate pads and the solder balls.
 45. The semiconductordevice of claim 25, wherein the encapsulant does not encroach into thefirst or second region of the second surface of the substrate.
 46. Thesemiconductor device of claim 25, wherein the substrate comprises aprinted circuit board.
 47. A semiconductor device assembly, comprising:a substrate with an opening formed therethrough between a first surfaceand a second surface, the opening being substantially centrally located,wherein the substrate comprises substrate pads formed on the secondsurface proximate the opening, trace terminals formed on the secondsurface such that the substrate pads are formed between the opening andthe trace terminals, and circuit traces extending from the substratepads through the substrate to the trace terminals; a semiconductor diesecured to the first surface of the substrate, the semiconductor dieincluding bond pads aligned with the opening; bond wires extending fromthe bond pads of the semiconductor die to corresponding substrate padsof the substrate, the corresponding contacts being located adjacent tothe opening; an encapsulant filling the opening and covering the bondwires and the corresponding substrate pads of the substrate, theencapsulant protruding beyond a plane in which the second surface of thesubstrate is located; and discrete conductive elements secured to thetrace terminals of the substrate such that the discrete conductiveelements are in electrical communication with the corresponding bondpads of the semiconductor die via the trace terminals, the circuittraces, the substrate pads and the bond wires.
 48. The semiconductordevice assembly of claim 47, wherein the discrete conductive elementsprotrude beyond the plane in which the second surface of the substrateis located.
 49. The semiconductor device assembly of claim 48, whereinthe discrete conductive elements comprise solder balls.
 50. Thesemiconductor device assembly of claim 48, wherein the discreteconductive elements protrude a same distance beyond the plane in whichthe second surface of the substrate is located as a distance theencapsulant protrudes beyond the plane.
 51. The semiconductor deviceassembly of claim 48, wherein the discrete conductive elements protrudea greater distance beyond the plane in which the second surface of thesubstrate is located than a distance the encapsulant protrudes beyondthe plane.
 52. The semiconductor device assembly of claim 48, furthercomprising: a carrier including terminals to which the discreteconductive elements are secured.
 53. A device, comprising: asemiconductor die comprising die pads along a center region of the die;a substantially planar package substrate of substantially uniformthickness comprising a first surface, a second surface and athrough-hole formed between the first and second surfaces and alignedwith the die pads, wherein the substrate comprises substrate pads formedon second surface proximate the through-hole, trace terminals formed onthe second surface such that the substrate pads are formed between thethrough-hole and the trace terminals, and circuit traces extending afrom the substrate pads through the substrate to the trace terminals;adhesive to adhere the die to the first surface of the substrate;conductive wires that are coupled between the substrate pads of thesubstrate and the die pads of the die through the through-hole;encapsulant that fills the through-hole and forms a protrusion, whereinthe protrusion extends a first distance below a plane defined by thesecond surface of the substrate; and solder balls disposed under thesecond surface of the substrate and electrically coupled to the die padsvia the trace terminals, the circuit traces, the substrate pads and theconductive wires, wherein the solder balls extend below the secondsurface by a second distance that is greater than the first distance.54. The device of claim 53, wherein the conductive wires are bond wires.55. The device of claim 54, wherein the die pads comprise first andsecond rows of die pads electrically coupled by the bond wires to firstand second rows of the substrate pads, respectively, adjacent to firstand second sides of the through-hole, respectively.
 56. The device ofclaim 55, wherein the first and second sides of the through-hole are theonly sides of the through-hole having substrate pads proximate thereto,the substrate comprises only one through-hole, and the through-holeexposes the die to the encapsulant from approximately one edge of thedie to another.
 57. The device of claim 53, wherein the first distanceis at least a majority of the second distance.
 58. The device of claim53, wherein the adhesive extends beyond a periphery of the die, andfurther comprising encapsulating material disposed on the first surfaceof the substrate and surrounding a periphery of the die.
 59. The deviceof claim 58, wherein the adhesive does not encroach above thethrough-hole.
 60. The device of claim 53, wherein the protrusion tapersfrom a center of the protrusion towards outer edges of the protrusion.61. The device of claim 53, wherein at least some of the solder ballsare at least partially disposed outside of any location underneath thedie.
 62. The device of claim 61, wherein most of the solder balls aredisposed underneath the die.
 63. The device of claim 53, wherein amajority of the solder balls are disposed underneath the die.
 64. Thedevice of claim 53, further comprising a PCB comprising connector padsto which the solder balls are soldered, wherein the connector pads areelectrically coupled via conductive traces to other electricalcomponents mounted to the PCB.
 65. The device of claim 64, wherein thethrough-hole exposes a region of the die to the encapsulant that extendsfrom one edge of the die to an opposite edge of the die.
 66. The deviceof claim 65, wherein the first distance is at least a majority of thesecond distance.
 67. The device of claim 53, wherein the substrate issufficiently rigid to maintain planarity in a region between outer edgesof the die and outer edges of the substrate.
 68. The device of claim 67,wherein the solder balls have a minimum pitch and at least one side ofthe peripheral region is at least as wide as the pitch.
 69. The deviceof claim 53, wherein the through-hole exposes a region of the die to theencapsulant that extends from one edge of the die to an opposite edge ofthe die.
 70. The device of claim 69, wherein the substrate is ofsufficient rigidity to maintain planarity in a peripheral region thatextends out from a periphery of the die to a periphery of the substrate.71. The device of claim 53, wherein a first three rows of the solderballs, parallel to the through-hole, are disposed beneath a first regionof the lower surface that extends between the through-hole and a firstedge of the substrate, and a second three rows of the solder balls,parallel to the through-hole, are disposed beneath a second region ofthe lower surface that extends between the through-hole and a secondedge, opposite the first edge, of the substrate.
 72. The device of claim71, wherein the encapsulant is substantially absent from beneath thefirst and second regions of the lower surface other than proximate thethrough-hole.
 73. The device of claim 53, further comprisingencapsulating material disposed on the first surface of the substrateand surrounding a periphery of the die.
 74. The device of claim 53,wherein the package substrate is a printed circuit board.